1. Field of the Invention
This invention relates to integrated circuit (IC) fabrication technology, and more particularly, to a method of fabricating a dual damascene structure in an IC device having multilevel interconnects.
2. Description of Related Art
In the fabrication of high-density IC devices, RC (resistance-capacitance) content is a major factor that affects the IC performance. The RC content is dependent on the electrical resistance of the metal interconnects in the IC device. Therefore, a metal with a low electrical resistance, such as copper, is preferably utilized to form the metal interconnects in IC devices.
Copper is not only low in electrical resistivity, but it also has high electron mobility and can be fabricated through the industry standard physical vapor deposition (PVD) or Electro-plating deposition or chemical-vapor deposition (CVD) process. Therefore, it is widely used in deep-submicron level IC fabrication. However, although copper has many such benefits, there are still some problems encountered when using copper in IC fabrication. For instance, copper is easily oxidized and eroded when exposed to a humid atmosphere. Moreover, it is difficult to use a dry-etching process for fine pattern definition on a copper-based metallization layer. A further drawback is copper's high diffusion coefficient that causes it to easily diffuse into silicon and form a copper/silicon alloy under low-temperature conditions. Additionally, copper bonds poorly with dielectrics and can easily diffuse through a dielectric layer when subjected to an electric field, thus undesirably resulting in a defect in the semiconductor structure and degradation of the reliability of the resultant IC device.
A solution to the foregoing problems is the use of what is known as a dual damascene structure, which combines a metal plug and an upper level of metallization layer into a single metallization structure in the dielectric layer separating the upper level of metallization layer from the bottom level of metallization layer in the multilevel interconnect structure. A dual damascene structure is conventionally formed by, for example, a first step of forming a dielectric layer over a semiconductor substrate; a second step of forming a combined void structure including a via hole and a trench at predefined locations in the dielectric layer; a third step of depositing metal such as copper into the combined void structure; and a final step of performing a CMP (chemical-mechanical polishing) process to planarize the resultant metallization layer, with the remaining part of the metallization layer serving as the intended dual damascene structure. Since no etching is involved during the foregoing process, the resultant dual damascene structure has enhanced pattern definition. Moreover, copper diffusion is prevented and adhesion between the metallization layer and the dielectric layer is stronger. In addition, a barrier layer is typically formed between the metallization layer and the dielectric layer so as to prevent ion diffusion from the metallization layer to the dielectric layer. Furthermore, a passivation layer is formed over the copper-based metallization layer to prevent the metallization layer from oxidizing.
A conventional method for fabricating a dual damascene structure in an integrated circuit is illustratively depicted in the following with reference to FIGS. 1A-1C.
Referring first to FIG. 1A, the dual damascene structure is constructed on a semiconductor substrate 100. A bottom level metallization layer 102 is formed, preferably from copper, at a predefined location in the substrate 100. Next, a topping layer 104 is formed over the substrate 100, and then a dielectric layer 106 is formed over the topping layer 104. The dielectric layer 106 and the topping layer 104 are selectively removed through a photolithographic and etching process to thereby form a combined void structure including a via hole 110 exposing the bottom level metallization layer 102 and a trench 108 above the via hole 110.
Referring further to FIG. 1B, in the subsequent step, a conformal barrier layer 112 is formed over the wafer in such a manner as to cover all the exposed surfaces of the wafer, including the topmost surface of the dielectric layer 106, the sidewalls of the trench 108 and the via hole 110, and the exposed surface of the bottom level metallization layer 102. Next, a metallization structure 114 is formed by depositing copper into the trench 108 and the via hole 110 and over the top surface of the conformal barrier layer 112.
Referring further to FIG. 1C, in the subsequent step, a chemical-mechanical polishing (CMP) process is performed on the wafer until the topmost surface of the dielectric layer 106 is exposed, whereby the surface parts of the metallization structure 114 and the conformal barrier layer 112 that lie above the topmost surface of the dielectric layer 106 are removed, with the remaining parts thereof planarized. Next, a passivation layer 122 is formed over the entire top surface of the wafer, covering all the exposed surfaces of the dielectric layer 106 and the remaining part of the metallization structure 114. The passivation layer 122 is preferably formed from silicon nitride or silicon carbide through a chemical vapor deposition (CVD) process. This passivation layer 122 can help prevent the metallization structure 114 from oxidizing and also can help prevent the copper atoms/ions in the metallization structure 114 from diffusing into the subsequently formed dielectric layer (not shown) over the metallization structure 114. The remaining part of the metallization structure 114 in the trench 108 and the via hole 110 then serves as the intended dual damascene structure, with the part in the via hole 110 serving as a metal plug and the part in the trench 108 serving as an upper level metallization layer in the multilevel-interconnect structure.
One drawback to the foregoing method, however, is that the use of silicon nitride or silicon carbide to form the passivation layer 122 results in poor adhesion between the passivation layer 122 and the metallization structure 114 due to accumulated stresses from the deposition process, which results in the passivation layer 122 easily peeling off from the top surface of the wafer, as the part indicated by reference numeral 124 in FIG. 1C. The resultant IC device thus has a reliability problem.